Exemplary embodiments of the present invention relate to a semiconductor device and an operation method thereof, more particularly, to a semiconductor device and an operation method thereof for securing a write recovery time.
A write recovery time is defined as from a time point of completion of write operation to a time point of stable storage of data to a cell of a semiconductor device without vulnerability to a pre-charge operation, which means amount of delay that must elapse after the completion of a valid write operation, before an active bank can be precharged. That is, the write recover time represents a minimum time requested to secure stored data on a cell of a semiconductor device after the completion of a valid write operation.
A conventional semiconductor device adjusts an input time of a pre-charge command to secure the write recovery time.
Meanwhile, as a semiconductor device operates at a high speed, internal signals of the semiconductor device may be incorrectly transferred due to a noise according to a Process, Voltage and Temperature (PVT).
For example, although a controller of a semiconductor device transfers sequentially a write command for a first bank and a pre-charge command for a second bank to perform a write operation of the first bank and a pre-charge operation of the second bank, the pre-charge command for the second bank may be corrupted and misidentified with a pre-charge command for the first bank due to a noise caused by the PVT, and the write command and the misidentified pre-charge command for the first bank may be sequentially transferred to the semiconductor device.
In such a case, since the first bank receives the write command and the misidentified pre-charge command sequentially, a write recovery time corresponding to the write command may not be secured.
That is, since the write command is correct command whereas the misidentified pre-charge command right after the write command is an incorrect command where the timing of the write recovery time is not reflected, a data to be stored according to the write operation may be corrupted.
Here, since a conventional semiconductor device does not detect whether or not a pre-charge command is misidentified, it is impossible to secure a write recovery time in a manner of adjusting an applying time of a pre-charge command.